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Hybrid Wafer Defect Detection and Segmentation Using Verilog-Based Image Preprocessing and Deep Learning Architectures.

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Bibliographic Details
Title:	Hybrid Wafer Defect Detection and Segmentation Using Verilog-Based Image Preprocessing and Deep Learning Architectures.
Authors:	Naik, Bukke Chandrababu¹ (AUTHOR) chandrababu@nitt.edu, Sevagan, S.¹ (AUTHOR) 108121028@nitt.edu, Kamalakannan, Bharath¹ (AUTHOR) 108121028@nitt.edu, Derllinraj, N.¹ (AUTHOR) 108121034@nitt.edu, Gopi, Varun P.¹ (AUTHOR) varun@nitt.edu
Source:	Arabian Journal for Science & Engineering (Springer Science & Business Media B.V. ). Apr2026, Vol. 51 Issue 8, p10989-11004. 16p.
Subject Terms:	Semiconductor defects, Computer hardware description languages, Field programmable gate arrays, Image enhancement (Imaging systems), *Deep learning
Abstract:	Wafer maps contain essential defect patterns that play a crucial role in identifying failures within the semiconductor manufacturing process. Traditional inspection techniques, including manual analysis or conventional machine learning approaches with handcrafted features, often yield suboptimal accuracy and are not scalable. To address these limitations, this article presents a hybrid methodology that integrates hardware acceleration with advanced deep learning-based models for the automated identification of wafer defects. Verilog-based image preprocessing routines were developed and verified for hardware suitability; however, FPGA deployment and evaluation remain as future work. The preprocessed data is utilized for both detection and segmentation tasks using a variety of deep learning architectures. Detection is performed using ResNet integrated with convolutional block attention modules (CBAM). For segmentation, a model based on the Dense, Residual, Attention, and Multiscale Feature Network (DRAM) is employed. All implementations are carried out using Python. These models are rigorously evaluated using multiple performance metrics to determine the most effective framework for robust defect detection. The experimental findings on a real wafer dataset validate that the proposed methodology achieves a detection accuracy of 99.69% and a segmentation accuracy of 99.04%, significantly outperforming existing approaches in both speed and reliability. [ABSTRACT FROM AUTHOR]
Database:	Energy & Power Source

Description
Abstract:	Wafer maps contain essential defect patterns that play a crucial role in identifying failures within the semiconductor manufacturing process. Traditional inspection techniques, including manual analysis or conventional machine learning approaches with handcrafted features, often yield suboptimal accuracy and are not scalable. To address these limitations, this article presents a hybrid methodology that integrates hardware acceleration with advanced deep learning-based models for the automated identification of wafer defects. Verilog-based image preprocessing routines were developed and verified for hardware suitability; however, FPGA deployment and evaluation remain as future work. The preprocessed data is utilized for both detection and segmentation tasks using a variety of deep learning architectures. Detection is performed using ResNet integrated with convolutional block attention modules (CBAM). For segmentation, a model based on the Dense, Residual, Attention, and Multiscale Feature Network (DRAM) is employed. All implementations are carried out using Python. These models are rigorously evaluated using multiple performance metrics to determine the most effective framework for robust defect detection. The experimental findings on a real wafer dataset validate that the proposed methodology achieves a detection accuracy of 99.69% and a segmentation accuracy of 99.04%, significantly outperforming existing approaches in both speed and reliability. [ABSTRACT FROM AUTHOR]
ISSN:	2193567X
DOI:	10.1007/s13369-025-10870-y