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An On-Chip Trainable and Scalable In-Memory ANN Architecture for AI/ML Applications.

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Title: An On-Chip Trainable and Scalable In-Memory ANN Architecture for AI/ML Applications.
Authors: Kumar, Abhash1 (AUTHOR) abhash2205@gmail.com, Beeraka, Sai Manohar1 (AUTHOR), Singh, Jawar2 (AUTHOR), Gupta, Bharat1 (AUTHOR)
Source: Circuits, Systems & Signal Processing. May2023, Vol. 42 Issue 5, p2828-2851. 24p.
Database: Mathematics Source
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  Data: <searchLink fieldCode="JN" term="%22Circuits%2C+Systems+%26+Signal+Processing%22">Circuits, Systems & Signal Processing</searchLink>. May2023, Vol. 42 Issue 5, p2828-2851. 24p.
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      – Type: doi
        Value: 10.1007/s00034-022-02237-7
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      – Code: eng
        Text: English
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            NameFull: Beeraka, Sai Manohar
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              Text: May2023
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              Y: 2023
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