Device-scaling constraints imposed by the van der Waals gap formed in two-dimensional materials.
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| Title: | Device-scaling constraints imposed by the van der Waals gap formed in two-dimensional materials. |
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| Authors: | Pourfath, Mahdi (AUTHOR), Grasser, Tibor (AUTHOR) |
| Source: | Science. 5/21/2026, Vol. 392 Issue 6800, p1-10. 10p. |
| Subjects: | Two-dimensional materials (Nanotechnology), Contact resistance (Materials science), Semiconductor junctions, Voltage control |
| Abstract: | Transistor miniaturization requires controlling gate leakage through ultrathin dielectrics and minimizing source-drain contact resistance. Although two-dimensional semiconductors offer excellent electrostatic control, their interfaces with gate dielectrics and contact metals often form a van der Waals (vdW) gap that affects device performance and acts as a tunneling barrier with a low dielectric constant. While this reduces dielectric leakage, it increases metal-channel contact resistance and introduces a parasitic series capacitance to the gate. We quantified the trade-off between leakage suppression and electrostatic and contact-resistance scaling limits. As a result of this trade-off, many insulators fail to meet scaling targets, and metal-channel contacts fall short of required resistances. Zipper-like interfaces, where quasi-covalent bonding removes the vdW gap without creating dangling bonds, offer a path toward ultrascaled transistor designs. Editor's summary: The contacts between two-dimensional semiconductors such as molybdenum disulfide with metals and insulators can create van der Waals gaps that can be detrimental to device performance. Pourfath and Grasser showed for several systems that these gaps form tunneling barriers with a low dielectric constant that can reduce leakage through the gate dielectric, but they also increase contact resistance with metals and add parasitic capacitance that lowers performance. Bridging these gaps with bonding networks that avoid dangling bonds can minimize the detrimental effects and improve device scaling. —Phil Szuromi INTRODUCTION: As conventional silicon technology approaches its scaling limits, continued transistor miniaturization increasingly depends on strong gate control over the channel. Two-dimensional (2D) semiconductors are therefore attractive because their atomically thin channels can, in principle, be controlled more effectively by the gate. At the same time, scaling requires low leakage through the gate insulator and low electrical resistance at the metal source and drain contacts of the transistor. In practice, however, interfaces formed by 2D materials differ from those in silicon devices and introduce new constraints. RATIONALE: At many interfaces involving 2D semiconductors, the materials do not form covalent bonds but rather are separated by a van der Waals (vdW) gap. The physical spacing between facing atomic planes is typically about 3 Å. Only part of this separation is electronically active for electrostatics and tunneling. This interfacial region plays a dual role: It adds a tunneling barrier that can suppress unwanted leakage current, but it also behaves like a low-capacitance layer in series with the gate insulator, which weakens the gate's control over the channel. At metal contacts, the same type of interface reduces carrier transmission and increases contact resistance. Understanding this trade-off is essential for assessing how far devices based on 2D materials can be scaled. RESULTS: We find that, although the atomic plane separation is ~3 Å, the electronically relevant, vacuum-like vdW gap is only ~1.4 Å and has a low effective permittivity of ~2. Because its permittivity is so low, this gap reduces the gate's electrostatic control far more than its atomic thickness alone might suggest. As a result, even this atomically thin separation makes it difficult to continue transistor scaling along established technology trends. At the same time, the vdW gap suppresses direct tunneling and can therefore reduce gate leakage. For metal contacts, the vdW gap acts as a thin tunneling barrier that reduces carrier transmission and increases the minimum achievable contact resistance, placing many vdW-bonded contacts above the required target values unless the gap is reduced or replaced by more covalent bonding. CONCLUSION: vdW-bonded interfaces therefore play a dual role: They can be beneficial for suppressing leakage, but they also weaken gate control and increase contact resistance, limiting transistor scaling even when the bulk gate insulator material itself has favorable properties. Interfaces engineered to reduce or eliminate the vdW gap through zipper-like, quasi-covalent bonding offer a route to maintain strong gate control while keeping leakage and contact resistance low in ultrascaled transistors based on 2D materials. Impact of the vdW gap on gate control and contacts.: Although facing atomic planes in 2D materials are separated by ~3 Å, the electronically relevant, vacuum-like vdW gap is ~1.4 Å and has an effective permittivity of ~2. This low-permittivity interfacial layer appears as a capacitance in series with the gate insulator (Cins), thereby reducing the overall gate capacitance and weakening electrostatic control of the channel. At the same time, the vdW gap suppresses direct tunneling, lowering the gate leakage current, but acts as a tunneling barrier at the metal-semiconductor interface, increasing the source-drain contact resistance (RSD). [ABSTRACT FROM AUTHOR] |
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| Database: | Psychology and Behavioral Sciences Collection |
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| Abstract: | Transistor miniaturization requires controlling gate leakage through ultrathin dielectrics and minimizing source-drain contact resistance. Although two-dimensional semiconductors offer excellent electrostatic control, their interfaces with gate dielectrics and contact metals often form a van der Waals (vdW) gap that affects device performance and acts as a tunneling barrier with a low dielectric constant. While this reduces dielectric leakage, it increases metal-channel contact resistance and introduces a parasitic series capacitance to the gate. We quantified the trade-off between leakage suppression and electrostatic and contact-resistance scaling limits. As a result of this trade-off, many insulators fail to meet scaling targets, and metal-channel contacts fall short of required resistances. Zipper-like interfaces, where quasi-covalent bonding removes the vdW gap without creating dangling bonds, offer a path toward ultrascaled transistor designs. Editor's summary: The contacts between two-dimensional semiconductors such as molybdenum disulfide with metals and insulators can create van der Waals gaps that can be detrimental to device performance. Pourfath and Grasser showed for several systems that these gaps form tunneling barriers with a low dielectric constant that can reduce leakage through the gate dielectric, but they also increase contact resistance with metals and add parasitic capacitance that lowers performance. Bridging these gaps with bonding networks that avoid dangling bonds can minimize the detrimental effects and improve device scaling. —Phil Szuromi INTRODUCTION: As conventional silicon technology approaches its scaling limits, continued transistor miniaturization increasingly depends on strong gate control over the channel. Two-dimensional (2D) semiconductors are therefore attractive because their atomically thin channels can, in principle, be controlled more effectively by the gate. At the same time, scaling requires low leakage through the gate insulator and low electrical resistance at the metal source and drain contacts of the transistor. In practice, however, interfaces formed by 2D materials differ from those in silicon devices and introduce new constraints. RATIONALE: At many interfaces involving 2D semiconductors, the materials do not form covalent bonds but rather are separated by a van der Waals (vdW) gap. The physical spacing between facing atomic planes is typically about 3 Å. Only part of this separation is electronically active for electrostatics and tunneling. This interfacial region plays a dual role: It adds a tunneling barrier that can suppress unwanted leakage current, but it also behaves like a low-capacitance layer in series with the gate insulator, which weakens the gate's control over the channel. At metal contacts, the same type of interface reduces carrier transmission and increases contact resistance. Understanding this trade-off is essential for assessing how far devices based on 2D materials can be scaled. RESULTS: We find that, although the atomic plane separation is ~3 Å, the electronically relevant, vacuum-like vdW gap is only ~1.4 Å and has a low effective permittivity of ~2. Because its permittivity is so low, this gap reduces the gate's electrostatic control far more than its atomic thickness alone might suggest. As a result, even this atomically thin separation makes it difficult to continue transistor scaling along established technology trends. At the same time, the vdW gap suppresses direct tunneling and can therefore reduce gate leakage. For metal contacts, the vdW gap acts as a thin tunneling barrier that reduces carrier transmission and increases the minimum achievable contact resistance, placing many vdW-bonded contacts above the required target values unless the gap is reduced or replaced by more covalent bonding. CONCLUSION: vdW-bonded interfaces therefore play a dual role: They can be beneficial for suppressing leakage, but they also weaken gate control and increase contact resistance, limiting transistor scaling even when the bulk gate insulator material itself has favorable properties. Interfaces engineered to reduce or eliminate the vdW gap through zipper-like, quasi-covalent bonding offer a route to maintain strong gate control while keeping leakage and contact resistance low in ultrascaled transistors based on 2D materials. Impact of the vdW gap on gate control and contacts.: Although facing atomic planes in 2D materials are separated by ~3 Å, the electronically relevant, vacuum-like vdW gap is ~1.4 Å and has an effective permittivity of ~2. This low-permittivity interfacial layer appears as a capacitance in series with the gate insulator (Cins), thereby reducing the overall gate capacitance and weakening electrostatic control of the channel. At the same time, the vdW gap suppresses direct tunneling, lowering the gate leakage current, but acts as a tunneling barrier at the metal-semiconductor interface, increasing the source-drain contact resistance (RSD). [ABSTRACT FROM AUTHOR] |
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| ISSN: | 00368075 |
| DOI: | 10.1126/science.aeb2271 |
