View in EDS

A sub–10-millisecond neural dynamical system based on phase-change memristors.

Saved in:
Bibliographic Details
Title: A sub–10-millisecond neural dynamical system based on phase-change memristors.
Authors: Cai, Lei (AUTHOR), Tao, Yaoyu (AUTHOR), Xie, Chenchen (AUTHOR), Yan, Longhao (AUTHOR), Li, Shiqian (AUTHOR), Shen, Ruihong (AUTHOR), Pan, Zelun (AUTHOR), Wang, Xile (AUTHOR), Wang, Bowen (AUTHOR), Shi, Daijing (AUTHOR), Zhu, Yihang (AUTHOR), Zhang, Teng (AUTHOR), Zhu, Yixin (AUTHOR), Li, Xi (AUTHOR), Song, Zhitang (AUTHOR), Huang, Ru (AUTHOR), Yang, Yuchao (AUTHOR)
Source: Science. 7/2/2026, Vol. 393 Issue 6806, p105-112. 8p.
Subjects: Memristors, Dynamical systems, Computer architecture, Real-time computing, Mathematical optimization, Three-dimensional modeling
Abstract: High-fidelity geometry for physical-world modeling demands real-time, dense, and differentiable deformation fields on manifolds. Neural dynamical systems (NDSs) using adaptive stepsize integration with embedded neural networks excel at these tasks but still suffer latency on the order of hundreds of milliseconds. In this work, we report a sub–10-millisecond NDS hardware leveraging the precisely controlled conductance drift of phase-change memristors and their multilevel compute-in-memory capabilities. We fabricated a 40-nanometer NDS chip for the challenging surface reconstruction tasks. Compared with state-of-the-art NDS hardware, our NDS design achieves a latency of 2.12 milliseconds (below 10 milliseconds) for single-iteration NDS computations with an error tolerance of 10−7 and delivers 3.82× to 36.27× faster speed while consuming 11.75× to 24.73× less power. The end-to-end NDS latency through hardware measurements and simulations outperformed graphics processing unit A100 by 50.38× to 478.18×. Editor's summary: One of the challenges of using a phase-change memristor (PCM) for analog computing is its natural conductance drift caused by structural relaxation. However, such drift could serve as a functional computing feature rather than as a limitation for a neural dynamical system (NDS) that synergizes the strengths of neural networks and the power of continuous-time dynamical systems for various complex physical world models. By exploiting two distinct characteristics of PCMs, precision-controlled conductance drift and multilevel conductance, Cai et al. demonstrated a hardware-algorithm codesign that delivered significant speed and power improvements over digital NDS accelerators (see the Perspective by Zheng and Valov). The custom chip enabled sub–10 millisecond low-latency NDS computation, supported complex three-dimensional modeling tasks, and achieved up to 5089 times speedup with much lower power consumption compared with state-of-the-art NDS accelerators. —Yury Suleymanov [ABSTRACT FROM AUTHOR]
Copyright of Science is the property of American Association for the Advancement of Science and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
Database: Psychology and Behavioral Sciences Collection
Description
Abstract:High-fidelity geometry for physical-world modeling demands real-time, dense, and differentiable deformation fields on manifolds. Neural dynamical systems (NDSs) using adaptive stepsize integration with embedded neural networks excel at these tasks but still suffer latency on the order of hundreds of milliseconds. In this work, we report a sub–10-millisecond NDS hardware leveraging the precisely controlled conductance drift of phase-change memristors and their multilevel compute-in-memory capabilities. We fabricated a 40-nanometer NDS chip for the challenging surface reconstruction tasks. Compared with state-of-the-art NDS hardware, our NDS design achieves a latency of 2.12 milliseconds (below 10 milliseconds) for single-iteration NDS computations with an error tolerance of 10−7 and delivers 3.82× to 36.27× faster speed while consuming 11.75× to 24.73× less power. The end-to-end NDS latency through hardware measurements and simulations outperformed graphics processing unit A100 by 50.38× to 478.18×. Editor's summary: One of the challenges of using a phase-change memristor (PCM) for analog computing is its natural conductance drift caused by structural relaxation. However, such drift could serve as a functional computing feature rather than as a limitation for a neural dynamical system (NDS) that synergizes the strengths of neural networks and the power of continuous-time dynamical systems for various complex physical world models. By exploiting two distinct characteristics of PCMs, precision-controlled conductance drift and multilevel conductance, Cai et al. demonstrated a hardware-algorithm codesign that delivered significant speed and power improvements over digital NDS accelerators (see the Perspective by Zheng and Valov). The custom chip enabled sub–10 millisecond low-latency NDS computation, supported complex three-dimensional modeling tasks, and achieved up to 5089 times speedup with much lower power consumption compared with state-of-the-art NDS accelerators. —Yury Suleymanov [ABSTRACT FROM AUTHOR]
ISSN:00368075
DOI:10.1126/science.aee6277