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Design of a low-power 32K CMOS programmable delay-line memory.

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Bibliographic Details
Title: Design of a low-power 32K CMOS programmable delay-line memory.
Authors: Dejhan, Kobchai, Demassieux, Nicolas, Colavin, Oswald
Source: IEEE Journal of Solid-State Circuits; February 1990, Vol. 25, p234-238, 5p
Database: Applied Science & Technology Source
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